In this previous article, we explored how to create flexible inference templates for both Simple Dual-Port (SDP) and True Dual-Port (TDP) RAMs. As part of that discussion, we covered a lengthy, yet useful, workaround to enable the ram_style attribute in Vivado using a string parameter. In this follow-up, we’ll take a closer look at alternative […]
FPGA RAM Inference Templates: Part 2 Read More »
Preface This article originally set out to compare my experiences in academia and industry, with the aim of offering graduate students some insight into which career path to pursue. However, as soon as I began reflecting on my academic journey, what started as a comparison quickly turned into a therapy session—complete with a rant about
Dispelling the Myths of Academia Read More »
Retiming is a powerful optimization used in synthesis and digital-circuit design to improve the maximum clock frequency. Retiming works by relocating registers from paths with sufficient slack into paths with timing violations, essentially sacrificing slack from some paths to improve the timing of others—a strategy often referred to as “stealing slack.” For example: In this
Is Retiming a Productivity Shortcut? Read More »
While serving on the banquet panel at the 2024 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, I was asked “if you could start your career over, what would you work on?” My answer was “I would rebuild FPGA synthesis tools from the ground up.” When I left academia, this was one of the projects I
It’s Time to Rethink FPGA Compilation Read More »
Welcome to StittHub, a site where innovation meets education! I’m Greg Stitt, and for over 16 years, I served as a professor in the Department of Electrical and Computer Engineering at the University of Florida. During my time in academia, I taught and performed research in the areas of hardware design, hardware/software co-design, machine learning,
Welcome to StittHub Read More »