FPGA tools are infamous for annoying inconsistencies. One of the most chaotic inconsistencies is initialization of on-chip RAMs, where every tool (and even each language within the same tool) uses different methods. Many designers rely on vendor-specific RAM initialization files (e.g., Intel MIF) combined with vendor-provided RAM IP. While that approach works for some, it […]
In this previous article, we explored how to create flexible inference templates for both Simple Dual-Port (SDP) and True Dual-Port (TDP) RAMs. As part of that discussion, we covered a lengthy, yet useful, workaround to enable the ram_style attribute in Vivado using a string parameter. In this follow-up, we’ll take a closer look at alternative
FPGA RAM Inference Templates: Part 2 Read More »
RAMs are a fundamental part of most digital designs, yet there’s still no widely adopted RTL template for inferring RAMs that works reliably across all FPGAs. As a result, many designers resort to manually instantiating RAM primitives or using vendor-specific IP cores. While this approach gets the job done, it’s often tedious and undermines portability—one
Portable RAM Inference Templates for FPGAs Read More »
Retiming is a powerful optimization used in synthesis and digital-circuit design to improve the maximum clock frequency. Retiming works by relocating registers from paths with sufficient slack into paths with timing violations, essentially sacrificing slack from some paths to improve the timing of others—a strategy often referred to as “stealing slack.” For example: In this
Is Retiming a Productivity Shortcut? Read More »
If you’ve worked with Verilog or SystemVerilog, you’ve likely encountered the term race condition—and, if you’re like most engineers, you may not fully understand why they happen or how to avoid them. If that’s the case, don’t worry; you’re certainly not alone. Even seasoned experts with decades of experience, myself included, occasionally run into race
Race Conditions: The Root of All Verilog Evil Read More »
If you’ve studied digital design, you have likely used a field-programmable gate array (FPGA) to implement custom circuits. This widespread use of FPGAs stems from their flexible and reconfigurable architecture, which can support potentially any register-transfer level (RTL) design. However, unless you have deployed a highly constrained FPGA application, you might not have considered how
Optimizing Hardware For FPGAs Read More »
Register-transfer-level (RTL) development is widely known to be considerably more difficult than developing with more common high-level languages. The primary reason for this increased difficulty lies in the necessity for hardware expertise to craft efficient designs. However, even seasoned hardware engineers encounter distinct challenges that diverge sharply from those encountered in software development. These challenges
RTL Code is Weird: Part 1 Read More »
While serving on the banquet panel at the 2024 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, I was asked “if you could start your career over, what would you work on?” My answer was “I would rebuild FPGA synthesis tools from the ground up.” When I left academia, this was one of the projects I
It’s Time to Rethink FPGA Compilation Read More »
In this article, we again explore the intricacies of register-transfer-level (RTL) coding, investigating several often-overlooked topics that frequently lead to pitfalls in design. We then discuss more general verification techniques that help identify these pitfalls, and others as soon as possible. To help connect these topics, we use the following example, which has a subtle,
RTL Pitfalls: Stop Initializing Signals, Start Testing Resets, and Use Assertions Read More »
After the positive reception of my initial post on recursive RTL, which sparked numerous insightful discussions, I’m excited to present Part 2. In this installment, I’ll delve into addressing common misunderstandings while also introducing an optimization technique for the adder tree discussed previously. Why not create an adder tree through iterative accumulation? This question emerged
You Can (and Should) Write Recursive RTL: Part 2 Read More »