RTL Code

Optimizing Hardware For FPGAs

If you’ve studied digital design, you have likely used a field-programmable gate array (FPGA) to implement custom circuits. This widespread use of FPGAs stems from their flexible and reconfigurable architecture, which can support potentially any register-transfer level (RTL) design. However, unless you have deployed a highly constrained FPGA application, you might not have considered how […]

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RTL Code is Weird: Part 1

Register-transfer-level (RTL) development is widely known to be considerably more difficult than developing with more common high-level languages. The primary reason for this increased difficulty lies in the necessity for hardware expertise to craft efficient designs. However, even seasoned hardware engineers encounter distinct challenges that diverge sharply from those encountered in software development. These challenges

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RTL Pitfalls: Stop Initializing Signals, Start Testing Resets, and Use Assertions

In this article, we again explore the intricacies of register-transfer-level (RTL) coding, investigating several often-overlooked topics that frequently lead to pitfalls in design. We then discuss more general verification techniques that help identify these pitfalls, and others as soon as possible. To help connect these topics, we use the following example, which has a subtle,

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You Can (and Should) Write Recursive RTL: Part 2

After the positive reception of my initial post on recursive RTL, which sparked numerous insightful discussions, I’m excited to present Part 2. In this installment, I’ll delve into addressing common misunderstandings while also introducing an optimization technique for the adder tree discussed previously. Why not create an adder tree through iterative accumulation? This question emerged

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You Can (and Should) Write Recursive RTL Code

Recursion, a fundamental concept in both software engineering and mathematics, offers powerful problem-solving capabilities by defining a problem in terms of itself. Yet, within the realm of register-transfer level (RTL) code, its potential remains largely untapped. Despite its numerous advantages, recursion is often dismissed or deemed impossible in RTL coding circles. A simple online search

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Timing Optimization Tutorial

If you only studied digital design in college, there’s a good chance you don’t have much experience with timing analysis, optimization, and closure. Most digital-design classes, especially at the undergraduate level, primarily focus on creating correct circuits without too much focus on achieving specific clock frequencies. Students then graduate and enter industry where they discover

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Design the Circuit, then Write the Code

Greg Stitt. Design the Circuit, then Write the Code. StittHub (Jan. 2024). https://stitt-hub.com/design-the-circuit-then-write-the-code/. Target audience: beginning/intermediate hardware designers, junior/senior engineering undergraduates There is one saying my former students probably got tired of me saying: “design the circuit, then write the code.” In other words, you should know what you want your synthesized circuit to look

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