If you’ve worked with Verilog or SystemVerilog, you’ve likely encountered the term race condition—and, if you’re like most engineers, you may not fully understand why they happen or how to avoid them. If that’s the case, don’t worry; you’re certainly not alone. Even seasoned experts with decades of experience, myself included, occasionally run into race […]
Race Conditions: The Root of All Verilog Evil Read More »
If you’ve studied digital design, you have likely used a field-programmable gate array (FPGA) to implement custom circuits. This widespread use of FPGAs stems from their flexible and reconfigurable architecture, which can support potentially any register-transfer level (RTL) design. However, unless you have deployed a highly constrained FPGA application, you might not have considered how
Optimizing Hardware For FPGAs Read More »
Register-transfer-level (RTL) development is widely known to be considerably more difficult than developing with more common high-level languages. The primary reason for this increased difficulty lies in the necessity for hardware expertise to craft efficient designs. However, even seasoned hardware engineers encounter distinct challenges that diverge sharply from those encountered in software development. These challenges
RTL Code is Weird: Part 1 Read More »
While serving on the banquet panel at the 2024 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, I was asked “if you could start your career over, what would you work on?” My answer was “I would rebuild FPGA synthesis tools from the ground up.” When I left academia, this was one of the projects I
It’s Time to Rethink FPGA Compilation Read More »
In this article, we again explore the intricacies of register-transfer-level (RTL) coding, investigating several often-overlooked topics that frequently lead to pitfalls in design. We then discuss more general verification techniques that help identify these pitfalls, and others as soon as possible. To help connect these topics, we use the following example, which has a subtle,
RTL Pitfalls: Stop Initializing Signals, Start Testing Resets, and Use Assertions Read More »
After the positive reception of my initial post on recursive RTL, which sparked numerous insightful discussions, I’m excited to present Part 2. In this installment, I’ll delve into addressing common misunderstandings while also introducing an optimization technique for the adder tree discussed previously. Why not create an adder tree through iterative accumulation? This question emerged
You Can (and Should) Write Recursive RTL: Part 2 Read More »
Recursion, a fundamental concept in both software engineering and mathematics, offers powerful problem-solving capabilities by defining a problem in terms of itself. Yet, within the realm of register-transfer level (RTL) code, its potential remains largely untapped. Despite its numerous advantages, recursion is often dismissed or deemed impossible in RTL coding circles. A simple online search
You Can (and Should) Write Recursive RTL Code Read More »
Despite reset logic not being the most exciting topic, I’ve been excited to write this article for some time, especially since this is one of the topics I never managed to fit into my lectures at UF. I’m excited because this post will shed light on the fact that there are widespread RTL coding styles
Crafting Clean Reset Logic Read More »
If you only studied digital design in college, there’s a good chance you don’t have much experience with timing analysis, optimization, and closure. Most digital-design classes, especially at the undergraduate level, primarily focus on creating correct circuits without too much focus on achieving specific clock frequencies. Students then graduate and enter industry where they discover
Timing Optimization Tutorial Read More »
If you are learning RTL coding, looking for a useful language reference, or if you just want to see my thoughts on how to write RTL code, I would highly recommend my following two GitHub repositories: Each tutorial is accompanied by detailed README files, offering insights into the recommended study order and highlighting key points
VHDL and SystemVerilog Tutorials Read More »