RAMs are a fundamental part of most digital designs, yet there’s still no widely adopted RTL template for inferring RAMs that works reliably across all FPGAs. As a result, many designers resort to manually instantiating RAM primitives or using vendor-specific IP cores. While this approach gets the job done, it’s often tedious and undermines portability—one […]
Portable RAM Inference Templates for FPGAs Read More »
Retiming is a powerful optimization used in synthesis and digital-circuit design to improve the maximum clock frequency. Retiming works by relocating registers from paths with sufficient slack into paths with timing violations, essentially sacrificing slack from some paths to improve the timing of others—a strategy often referred to as “stealing slack.” For example: In this
Is Retiming a Productivity Shortcut? Read More »
If you’ve studied digital design, you have likely used a field-programmable gate array (FPGA) to implement custom circuits. This widespread use of FPGAs stems from their flexible and reconfigurable architecture, which can support potentially any register-transfer level (RTL) design. However, unless you have deployed a highly constrained FPGA application, you might not have considered how
Optimizing Hardware For FPGAs Read More »
Register-transfer-level (RTL) development is widely known to be considerably more difficult than developing with more common high-level languages. The primary reason for this increased difficulty lies in the necessity for hardware expertise to craft efficient designs. However, even seasoned hardware engineers encounter distinct challenges that diverge sharply from those encountered in software development. These challenges
RTL Code is Weird: Part 1 Read More »
While serving on the banquet panel at the 2024 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, I was asked “if you could start your career over, what would you work on?” My answer was “I would rebuild FPGA synthesis tools from the ground up.” When I left academia, this was one of the projects I
It’s Time to Rethink FPGA Compilation Read More »