Register-transfer-level (RTL) development is widely known to be considerably more difficult than developing with more common high-level languages. The primary reason for this increased difficulty lies in the necessity for hardware expertise to craft efficient designs. However, even seasoned hardware engineers encounter distinct challenges that diverge sharply from those encountered in software development. These challenges […]
RTL Code is Weird: Part 1 Read More »
While serving on the banquet panel at the 2024 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, I was asked “if you could start your career over, what would you work on?” My answer was “I would rebuild FPGA synthesis tools from the ground up.” When I left academia, this was one of the projects I
It’s Time to Rethink FPGA Compilation Read More »
If you only studied digital design in college, there’s a good chance you don’t have much experience with timing analysis, optimization, and closure. Most digital-design classes, especially at the undergraduate level, primarily focus on creating correct circuits without too much focus on achieving specific clock frequencies. Students then graduate and enter industry where they discover
Timing Optimization Tutorial Read More »