In this previous article, we explored how to create flexible inference templates for both Simple Dual-Port (SDP) and True Dual-Port (TDP) RAMs. As part of that discussion, we covered a lengthy, yet useful, workaround to enable the ram_style attribute in Vivado using a string parameter. In this follow-up, we’ll take a closer look at alternative […]
FPGA RAM Inference Templates: Part 2 Read More »
Retiming is a powerful optimization used in synthesis and digital-circuit design to improve the maximum clock frequency. Retiming works by relocating registers from paths with sufficient slack into paths with timing violations, essentially sacrificing slack from some paths to improve the timing of others—a strategy often referred to as “stealing slack.” For example: In this
Is Retiming a Productivity Shortcut? Read More »
Register-transfer-level (RTL) development is widely known to be considerably more difficult than developing with more common high-level languages. The primary reason for this increased difficulty lies in the necessity for hardware expertise to craft efficient designs. However, even seasoned hardware engineers encounter distinct challenges that diverge sharply from those encountered in software development. These challenges
RTL Code is Weird: Part 1 Read More »
In this article, we again explore the intricacies of register-transfer-level (RTL) coding, investigating several often-overlooked topics that frequently lead to pitfalls in design. We then discuss more general verification techniques that help identify these pitfalls, and others as soon as possible. To help connect these topics, we use the following example, which has a subtle,
RTL Pitfalls: Stop Initializing Signals, Start Testing Resets, and Use Assertions Read More »