Verification

Race Conditions: The Root of All Verilog Evil

/ Leave a Comment / RTL Code, Verification /

If you’ve worked with Verilog or SystemVerilog, you’ve likely encountered the term race condition—and, if you’re like most engineers, you may not fully understand why they happen or how to avoid them. If that’s the case, don’t worry; you’re certainly not alone. Even seasoned experts with decades of experience, myself included, occasionally run into race […]

Race Conditions: The Root of All Verilog Evil Read More »

RTL Pitfalls: Stop Initializing Signals, Start Testing Resets, and Use Assertions

/ Reset, RTL Code, Uncategorized, Verification /

In this article, we again explore the intricacies of register-transfer-level (RTL) coding, investigating several often-overlooked topics that frequently lead to pitfalls in design. We then discuss more general verification techniques that help identify these pitfalls, and others as soon as possible. To help connect these topics, we use the following example, which has a subtle,

RTL Pitfalls: Stop Initializing Signals, Start Testing Resets, and Use Assertions Read More »